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Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing | IEEE Conference Publication | IEEE Xplore

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing

Publisher: IEEE

Abstract:

FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementat...View more

Abstract:

FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of quasi-cyclic (QC) LDPC codes that takes advantage of the high bandwidth of the embedded memory blocks (called Block RAMs in a Xilinx FPGA) by packing multiple messages into the same word. We describe a vectorized overlapped message passing algorithm that results in 3.5times to 5.5times speedup over state-of-the-art FPGA implementations in literature.
Date of Conference: 20-24 April 2009
Date Added to IEEE Xplore: 23 June 2009
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: Nice, France

References

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