Power gating design for standard-cell-like structured ASICs | IEEE Conference Publication | IEEE Xplore

Power gating design for standard-cell-like structured ASICs


Abstract:

Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption bec...Show More

Abstract:

Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a power gated design flow mostly using existing standard cell design tools. We can configure PGVCLBs in a design to implement fine-grained power gating, coarse-grained/cluster-based power gating or even distributed sleep transistor network (DSTN). With fine-grained power gating, we can achieve 52% leakage reduction on average with only 8% area and 17% delay overheads when compared to the data obtained using a non-power-gated library.
Date of Conference: 08-12 March 2010
Date Added to IEEE Xplore: 29 April 2010
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Conference Location: Dresden, Germany

References

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