Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation | IEEE Conference Publication | IEEE Xplore

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation


Abstract:

The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO2 or SiON based technolo...Show More

Abstract:

The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO2 or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent variability. Conventional reliability margins, based on accelerated stress measurements on individual transistors, are no longer sufficient nor adequate for analog circuit design. As a means to find more accurate, circuit-dependent reliability margins, advanced degradation effect models are reviewed and an efficient method for stochastic circuit reliability simulation is discussed. Also, an example 6-bit 32nm current-steering digital-to-analog converter is studied. Experiments demonstrate how the proposed simulation tool, combined with novel design techniques, can provide an up to 89% better area-power product of the analog part of the circuit under study, while still guaranteeing a 99.7% yield over a lifetime of 5 years.
Date of Conference: 14-18 March 2011
Date Added to IEEE Xplore: 05 May 2011
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Conference Location: Grenoble, France

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