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An instruction scratchpad memory allocation for the precision timed architecture | IEEE Conference Publication | IEEE Xplore

An instruction scratchpad memory allocation for the precision timed architecture


Abstract:

This work presents a static instruction allocation scheme for the precision timed architecture's (PRET) scratchpad memory. Since PRET provides timing instructions to cont...Show More

Abstract:

This work presents a static instruction allocation scheme for the precision timed architecture's (PRET) scratchpad memory. Since PRET provides timing instructions to control the temporal execution of programs, the objective of the allocation scheme is to ensure that the explicitly specified temporal requirements are met. Furthermore, this allocation incorporates instructions from multiple hardware threads of the PRET architecture. We formulate the allocation as an integer-linear programming problem, and we implement a tool that takes binaries, constructs a control-flow graph, performs the allocation, rewrites the binary with the new allocation, and generates an output binary for the PRET architecture. We carry out experiments on a subset of a modified version of the Malardalen benchmarks to show the benefits of performing the allocation across multiple threads.
Date of Conference: 12-16 March 2012
Date Added to IEEE Xplore: 03 April 2012
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Conference Location: Dresden, Germany

References

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