An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.