New product development using nanometer semiconductor technologies require high-quality BIST solutions able to uncover dynamic faults. Most existing solutions rely on test-per-scan BIST, for high fault coverage. However, reconfiguration, in test mode, may significantly modify delays in signal paths, thus reducing the degree of confidence of dynamic fault coverage values. The purpose of this paper is to present a new high-quality test-per-clock BIST methodology for sequential digital systems. The proposed BIST methodology is an extension to sequential systems of the masked-based (or m-BIST) methodology. Determinism in test patterns (to uncover random-pattern resistant faults) is inserted with a low-intrusion scheme, in which the sequential behavior is preserved, and a bit-flipping technique is used. Functional-oriented patterns lead to high coverage of structural faults. Both academic (VeriDOS, ASCOPA) and commercial (Design Visiontrade Verifaulttrade tools are used to implement the methodology, which is demonstrated with an industrial design, the PIC controller of an electric static power meter. The methodology has been incorporated in the industrial partner design flow