Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance | IEEE Conference Publication | IEEE Xplore

Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance


Abstract:

The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degra...Show More

Abstract:

The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures due to parameter variations, and discuss test methodologies to test for process variation induced failures. Next, we describe two different self-repairing techniques-at the circuit level, using adaptive body biasing and at the architecture level, using built-in-self-test (BIST), redundancy and address remapping. The discussed self-repair mechanisms can improve design yield much beyond what can be achieved using row/column redundancy and error correcting codes (ECC) alone.
Date of Conference: 11-13 April 2007
Date Added to IEEE Xplore: 04 September 2007
ISBN Information:
Conference Location: Krakow, Poland

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