Countermeasures against side-channel attacks of cryptographic circuits have become of great concern when designing cryptographic and other sorts of circuits requiring secure handling of data. This paper suggests using subthreshold implementation for protection against power analysis attacks and presents a comparative analysis of a standard static CMOS 8-bit full adder cell, simulated in a 90 nm CMOS process, operating in the subthreshold and superthreshold region. A comparison of the correlation between input data and instantaneous power consumption is done. Circuit simulation and statistical analysis show that subthreshold operation gives orders of magnitude lower correlation between power consumption and data.