Abstract:
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constr...Show MoreMetadata
Abstract:
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.
Published in: 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
Date of Conference: 15-17 April 2009
Date Added to IEEE Xplore: 29 May 2009
ISBN Information: