An effective silicon debug and diagnosis process has to be supported by on-chip hardware structures, stimulation equipments and software tools for analysis. In this paper, the characteristics of a software tool for memory failure analysis are presented; this tool takes into account the memory topology and the executed memory test, and returns both syndrome and shape-based failure statistics. Furthermore, it allows the cumulative analysis over many memory cuts inside a die, a wafer or a lot. The results obtained for embedded SRAMs tested using March test algorithms are presented, demonstrating the capability of the tool in underlining manufacturing process weaknesses and systematic constructive marginalities.