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Design-for-Test method for high-speed ADCs: Behavioral description and optimization | IEEE Conference Publication | IEEE Xplore

Design-for-Test method for high-speed ADCs: Behavioral description and optimization


Abstract:

This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at t...Show More

Abstract:

This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.
Date of Conference: 13-15 April 2011
Date Added to IEEE Xplore: 31 May 2011
ISBN Information:
Conference Location: Cottbus, Germany

References

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