Abstract:
Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is present...Show MoreMetadata
Abstract:
Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.
Published in: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Date of Conference: 13-15 April 2011
Date Added to IEEE Xplore: 31 May 2011
ISBN Information: