In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it is necessary to swap the nodes and the edges in the signal flow graph. After executing this action the result is a signal flow plan. A value table exhibits the coding of the whole circuit. Then the so called module view is used to get the familiar compact display and neighborhood relations are repeated once more, the resolution method is used. It is observed that in digital circuits, undefined results can occur but these must be avoided in safety critical circuits. These events have to be secured in practice by costly and expensive verification and testing. In order to deal with the problem now, the structure preserving modeling has to be understood, since this is the only way to achieve a one-purpose, qualitative and cost effective search for errors.