Abstract:
Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detec...Show MoreMetadata
Abstract:
Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. The paper at hand presents and evaluates a Design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95%) without too much loss of fault information at a reasonable amount of control overhead. The approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68%.
Published in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Date of Conference: 19-21 April 2017
Date Added to IEEE Xplore: 29 May 2017
ISBN Information:
Electronic ISSN: 2473-2117