This paper presents a formal approach to verify and debug division circuits. The proposed technique is based on a reverse-engineering mechanism where a high-level model of the gate-level implementation is obtained and then an intermediate representation of the specification is introduced. This process makes equivalence checking between two models possible. The main advantage of this representation is the fact that the specification is dynamically changed according to the information obtained from the implementation. At the end, if two updated models are not equivalent, possible bugs can be localized and then corrected automatically by analyzing the difference. Experimental results show the robustness of the proposed approach in comparison with other contemporary methods in terms of the run time execution. The results also reveal that up to two orders of magnitude of average speedup can be obtained compared with the state-of-the-art.