High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases path delay, and thus might result in timing errors, such testing induces unnecessary yield loss in the deep sub-micron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low capture power oriented X-filling methods assign logic values to unspecified bits in test cubes to reduce the number of transitions on FFs. However, our goal is to reduce the number of transitions on internal signal lines. In this paper, we propose a low capture power oriented X-filling method iteratively using a Partial MaxSAT Solver which reduces the number of transitions on as many internal signal lines as possible. Experimental results show that our proposed method reduced the numbers of capture-unsafe test vectors and unsafe faults compared with conventional methods.