Abstract:
To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into t...Show MoreMetadata
Abstract:
To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.
Published in: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Date of Conference: 02-04 October 2019
Date Added to IEEE Xplore: 21 October 2019
ISBN Information: