As process technology dimensions shrink, manufacturing defect density is increasing, adversely impacting product yield. Products have typically built redundancy and repair features in SRAM. Register File arrays (RFs) can also benefit from redundancy and repair. There are various types of repair techniques used in SRAMs today which can also be employed on RFs. However all known techniques (column, row, 1-bit, multi-bit) incur a performance loss of at least two gate delays due to the addition of logic either on the memory address path or on the read output path. This paper describes a row repair scheme that incurs virtually no performance penalty. In simulations conducted in recent process nodes, we noted a performance impact of less than half a gate delay