LDPC codes are widely used in wireless communication systems for reliable data transmission due to their excellent error correction capabilities. SRAM-FPGAs are a popular option for the implementation of LDPC decoders due to their excellent computing capabilities and re-configurability. However, when applied in critical environments, e.g. space platforms, the SRAM-FPGA based LDPC decoders will suffer single-event upsets (SEUs) that can cause failures and disrupt communications. Therefore, analyzing the reliability of LDPC decoders to SEUs on the FPGA is important. This paper first analyzes the effects of SEUs on different parts of the FPGA implemented LDPC decoder based on the module functions, including the influence of the parallelism on the decoder reliability. Then fault injection experiments are performed to validate the conclusions of the analysis. Experiment results show that about 98% of SEUs on the configuration memories can be tolerated by the decoder itself, and the modules with more interconnections are less robust to SEUs. In addition, the reliability of LDPC decoders decreases for lower levels of parallelism due to the larger computation load of each unit. These results will be a valuable input to design efficient SEU protection schemes for LDPC decoders.