Abstract:
Complex digital components such as high performance CPUs are increasingly used in embedded systems with major robustness requirements. Early robustness evaluations, and e...Show MoreMetadata
Abstract:
Complex digital components such as high performance CPUs are increasingly used in embedded systems with major robustness requirements. Early robustness evaluations, and evaluations all along the development phases, are necessary when designing such systems to quickly converge towards the expected dependability level. These evaluations must take into account both the hardware platform and the application software, but at a time when the real application software is not yet available. First evaluations must therefore rely on expected characteristics of the target software and some knowledge about the robustness of similar programs. In this context, we propose a robustness evaluation methodology based on a set of metrics quantified using high-level software profiling and exploited to compute derating factors. We show that the early predictions are very close to results obtained from lengthy fault injections performed on the actual hardware platform, and still better when several metrics are combined with the usual consideration of data lifetime. We also discuss the impact of the compilation options on the quality of the evaluations.
Published in: 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Date of Conference: 08-10 October 2024
Date Added to IEEE Xplore: 20 November 2024
ISBN Information: