A new technique is presented for testing all possible faults in the interconnects of an arbitrary design implemented into air FPGA. The fault list includes all bridging faults between all pairs of nets in the design, as well as multiple stuck-at and open faults. Test configurations are obtained by modifying the configuration of logic blocks. The test vector and configuration generation complexity of this method is very small. As presented in the paper, less than 20 test configurations are required in order to detect all the faults, more than 100 billion, for the largest design mapped into the largest commercially available FPGA device, achieving 100% fault coverage.