Overcoming the low cell current bottleneck of 3D NAND flash memory array with novel device design | IEEE Conference Publication | IEEE Xplore

Overcoming the low cell current bottleneck of 3D NAND flash memory array with novel device design


Abstract:

The 3D NAND technology promises to extend the incredible growth of the bit-density of NAND flash memory over the next decade with the increased number of vertical layers ...Show More

Abstract:

The 3D NAND technology promises to extend the incredible growth of the bit-density of NAND flash memory over the next decade with the increased number of vertical layers (Fig. 1(a)). The ON-current of the memory cell (i.e., cell current), however, will be reduced significantly with the increased number of layers due to the increased series resistance of the vertical NAND string (Fig. 1(b)). Since memory cells in 3D NAND structure have polycrystalline silicon (poly-Si) with undoped source and drain (S/D), the cell current of the state-of-the-art 3D NAND technology is already low. The lower cell current causes sensing errors during the read operation of the memory array. Thus, the cell current problem can be a serious bottleneck to the future generation of the 3D NAND flash memory. The objective of this paper is to numerically explorer the bottleneck to the lower cell current in the 3D NAND structure. In addition, we propose and numerically evaluate three new device design ideas to enhance the cell current in the future generation of the 3D NAND flash memory.
Date of Conference: 25-28 June 2023
Date Added to IEEE Xplore: 24 July 2023
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Conference Location: Santa Barbara, CA, USA

References

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