The recent development of increasingly successful artificial intelligence applications have determined an unprecedented demand for optimized hardware for data-intensive computing. The currently employed device architecture, which relies on the separation between computing and memory units, requires frequent data transfers, causing energy inefficiencies and increased latency. A promising approach to solve this problem is represented by the Logic-in-Memory (LiM) architecture 1 , which aims at drastically reducing data transfer by relying on computing units that are also able to locally store information. A LiM enabling technology should be CMOS compatible and fully scalable. In recent years it was shown that, by recurring to an independently-gated Schottky-Barrier Field Effect Transistor (SB-FET), it is possible to obtain reconfigurable transistors that can show both n- and p-behavior without the need of doping 2 : while slightly increasing the complexity of the single transistor, this design allows to realize polymorphic logic gates with a reduced footprint with respect to the classic CMOS architecture 3 . When equipped with a memory element, such as a ferroelectric layer, this approach could prove promising for the realization of densely packed, adaptable LiM hardware. Here we explore the integration of a thin Hf 0.5 Zr 0.5 O 2 (HZO) layer into a Double-Top-Gated (DTG) SB-FET, a device where two polarity gates (PG) are located onto the two Schottky Barriers. This design is explicitly chosen to obtain a ferroelectric layer just in proximity of the Schottky Barrier areas, as shown in Fig. 1a , by exploiting the property of HZO of crystallizing into such a phase only when in contact with specific metals, like Pd or TiN. This allows us to investigate how a ferroelectric HZO phase can influence the injection of carriers, without modifying the channel transport properties. HZO also offers the advantage of being ALD- and CMOS-compatible and has already been shown to be pro...