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A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder | IEEE Conference Publication | IEEE Xplore

A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder


Abstract:

This paper presents a 2048 bit, rate 1/2 soft decision decoder for a new class of codes known as turbo Gallager codes. The decoder can support up to 1 Gbit/s code rate an...Show More

Abstract:

This paper presents a 2048 bit, rate 1/2 soft decision decoder for a new class of codes known as turbo Gallager codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 /spl mu/m standard-cell CMOS technology.
Date of Conference: 31 August 2004 - 03 September 2004
Date Added to IEEE Xplore: 20 September 2004
Print ISBN:0-7695-2203-3
Conference Location: Rennes, France

References

References is not available for this document.