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Multi-pipeline implementations of real-time vector DFT | IEEE Conference Publication | IEEE Xplore

Multi-pipeline implementations of real-time vector DFT


Abstract:

The article is devoted to creating a complete methodology for automatic synthesis of real-time FFT-processors at structural level under the given restrictions: speed of i...Show More

Abstract:

The article is devoted to creating a complete methodology for automatic synthesis of real-time FFT-processors at structural level under the given restrictions: speed of input data receipt, structure of the computing element, and the time of the butterfly operation execution. The suggested approach involves creating parallel-pipeline structures for fixed radix FFT and for modified split radix FFT algorithms. The structures employed in the design show good possibilities for scaling the degree of parallelization, thus changing the overall throughput of the system. They are particularly suited for implementing in programmable logic basis (FPGA).
Date of Conference: 31 August 2004 - 03 September 2004
Date Added to IEEE Xplore: 20 September 2004
Print ISBN:0-7695-2203-3
Conference Location: Rennes, France

References

References is not available for this document.