Scalable and area efficient concurrent interleaver for high throughput turbo-decoders | IEEE Conference Publication | IEEE Xplore

Scalable and area efficient concurrent interleaver for high throughput turbo-decoders


Abstract:

Parallel turbo decoder architectures have recently been proposed to reach high-throughput channel decoding capacity. However, the implementation of the underlying paralle...Show More

Abstract:

Parallel turbo decoder architectures have recently been proposed to reach high-throughput channel decoding capacity. However, the implementation of the underlying parallel interleaving subsystem suffers from memory access conflicts; those translate into logic overhead and critical path issues which are blocking factors for handheld system-on-chip solutions. In this paper, we explore several architecture and VLSI design strategies that drastically reduce the logic overhead and data-path delays of concurrent interleaving architectures. A stalling mechanism is introduced that reduces the interleaving subsystem die area and improves the architecture scalability with respect to the number of MAP producers. ASIC synthesis results in 0.18/spl mu/m and 0.13/spl mu/m CMOS STMicroelectronics technologies demonstrate the efficiency of the proposed VLSI concurrent interleaving architecture.
Date of Conference: 31 August 2004 - 03 September 2004
Date Added to IEEE Xplore: 20 September 2004
Print ISBN:0-7695-2203-3
Conference Location: Rennes, France

References

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