Loading [a11y]/accessibility-menu.js
Diminished-1 modulo 2/sup n/ + 1 squarer design | IEEE Conference Publication | IEEE Xplore

Diminished-1 modulo 2/sup n/ + 1 squarer design


Abstract:

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in c...Show More

Abstract:

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2/sup n/ + 1. To avoid using (n + 1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2/sup n/ + 1 arithmetic applications. In this paper, for the first time in the open literature, we formally derive modulo 2/sup n/ + 1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.
Date of Conference: 31 August 2004 - 03 September 2004
Date Added to IEEE Xplore: 20 September 2004
Print ISBN:0-7695-2203-3
Conference Location: Rennes, France

References

References is not available for this document.