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A novel VLSI architecture to implement region merging algorithm for image segmentation | IEEE Conference Publication | IEEE Xplore

A novel VLSI architecture to implement region merging algorithm for image segmentation


Abstract:

This paper describes VLSI architecture for the region-merging algorithm for image segmentation applications. This algorithm uses the region adjacency graph (RAG), which r...Show More

Abstract:

This paper describes VLSI architecture for the region-merging algorithm for image segmentation applications. This algorithm uses the region adjacency graph (RAG), which represents regions and their edges. The final segmentation provided by the RAG represents localized contours or surfaces. The architecture is proposed by making use of the concepts of parallelism and pipelining in order to improve the performance in terms of speed. The architecture has been coded in Verilog and synthesized using Synplify tools for FPGA implementation.
Date of Conference: 31 August 2004 - 03 September 2004
Date Added to IEEE Xplore: 20 September 2004
Print ISBN:0-7695-2203-3
Conference Location: Rennes, France

References

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