Abstract:
At-speed scan testing is becoming more and more popular in the semiconductor industry, as the relevance of delay-induced defects increases with CMOS process scaling and c...Show MoreMetadata
Abstract:
At-speed scan testing is becoming more and more popular in the semiconductor industry, as the relevance of delay-induced defects increases with CMOS process scaling and consequent IC complexity growth. This paper reports an industrial experience that demonstrate that at-speed transition fault testing is a crucial manufacturing step also for designs fabricated in mature processes and characterized by rather low working frequency, at least for highly reliable applications, such as automotive electronics and avionics. We present the identification of a timing- related defect on faulty parts and we discuss the application of at-speed scan testing which allowed us to achieve zero ppm final defect level after tests. The design was a serial communication receiver featuring an internal RC oscillator with 15 MHz typical oscillating frequency, fabricated in 0.8 mum CMOS technology.
Published in: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Date of Conference: 29-31 August 2007
Date Added to IEEE Xplore: 08 October 2007
ISBN Information: