A characterization of instruction-level error derating and its implications for error detection | IEEE Conference Publication | IEEE Xplore

A characterization of instruction-level error derating and its implications for error detection


Abstract:

In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by ...Show More

Abstract:

In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which computation on incorrect values can result in correct computation. We characterize the instruction-level derating that occurs in the SPEC CPU2000 INT benchmarks, classifying it (by source) into six categories: value comparison, sub-word operations, logical operations, overflow/precision, lucky loads, and dynamically-dead values. We also characterize the temporal nature of this derating, demonstrating that the effects of a fault persist in architectural state long after the last time they are referenced. Finally, we demonstrate how this characterization can be used to avoid unnecessary error recoveries (when a fault will be masked by software anyway) in the context of a dual modular redundant (DMR) architecture.
Date of Conference: 24-27 June 2008
Date Added to IEEE Xplore: 23 September 2008
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Conference Location: Anchorage, AK, USA

References

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