Abstract:
A new topology of a three-phase six-levels inverter is proposed in this paper. Two objectives are aimed in this new topology. The first one is to cancel the maximum of su...Show MoreMetadata
Abstract:
A new topology of a three-phase six-levels inverter is proposed in this paper. Two objectives are aimed in this new topology. The first one is to cancel the maximum of successive low-rank harmonics, with the minimum number of switching. The second objective is to cancel the homopolar voltage (sum of the three output voltages of the inverter).This double cancellation (low-rank successive harmonics and homopolar voltage) is achieved by using Pulse Width and Height Modulation (PWHM).In the proposed inverter, harmonics are successively cancelled, from 2 to 10. The rank of the first non-cancelled harmonic is 11. It amplitude is only 8% of the fundamental magnitude. Simulation results have demonstrated that the Total Harmonic Distortion (THD) voltage is only 15.22%, with only 12 switching states per period. The low switching frequency of the semiconductors (1.5 switches per period) reduces inverter power losses, thus improving efficiency. Analytical comparisons show that the proposed topology is competitive, with fewer power switches and control circuits than conventional topologies.
Published in: 2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)
Date of Conference: 14-16 October 2024
Date Added to IEEE Xplore: 13 December 2024
ISBN Information: