Abstract:
A power efficient 5-bit parallel comparator analogue to digital converter has been innovated and highlighted in this paper. The block diagram of the converter is provided...Show MoreMetadata
Abstract:
A power efficient 5-bit parallel comparator analogue to digital converter has been innovated and highlighted in this paper. The block diagram of the converter is provided by two schematic blocks. One of them is represented by a comparator and the other by digital encoder. In this mode, the speed of the encoder gets increased due to the pressure applied on the encoder through the manipulation of the modified form of preferential cascade voltage switch logic. The vital function of the aforesaid encoder is to accomplish transformation of thermometer code to Gray code and to minimise bubble errors and ensure meta-stability in the circuit. The 5-bit parallel comparator is designed and fabricated by using 180 nm CMOS technology at a supply voltage of ±0.85 V. The simulation results thus obtained in the above process, have been displayed at a sampling frequency of 5 GS/s and power dissipation of 23.29 mW respectively.
Published in: 2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)
Date of Conference: 28-30 June 2018
Date Added to IEEE Xplore: 04 April 2019
ISBN Information: