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Formal approach to synthesis of a test controller | IEEE Conference Publication | IEEE Xplore

Formal approach to synthesis of a test controller


Abstract:

In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level design...Show More

Abstract:

In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a finite state machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.
Date of Conference: 27-27 May 2004
Date Added to IEEE Xplore: 26 July 2004
Print ISBN:0-7695-2125-8
Conference Location: Brno, Czech Republic

References

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