Today's systems-on-chip have reached a complexity that demands high-level modelling for both design and verification. By raising the level of abstraction and supporting seamlessness in the methodology new design flows increases the productivity. High level models described on the basis of the C/C++ language family are widely used. Introducing a new flow based on the SDL SystemC allows reuse of such legacy models. A refinement method and a supporting framework are presented to integrate C-code for software and hardware components into a system level model. The focus of the presentation is on the multilevel model support of the framework.