A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications | IEEE Conference Publication | IEEE Xplore

A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications


Abstract:

A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is ...Show More

Abstract:

A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.
Date of Conference: 27-30 August 2007
Date Added to IEEE Xplore: 23 May 2008
ISBN Information:
Conference Location: Seville, Spain

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