For very high frequency applications feedback is not a suitable technique to be employed. In order to achieve high gain and large bandwidth, several open-loop stages are cascaded. In this paper we show that it is possible to improve the bandwidth of a cascaded amplifier, given constraints on input resistance, load capacitance and total bias current, by tapering the size of each amplifier stage. The technique is suitable for both MOS and BJT technologies, with or without the use of voltage followers to drive the load. A Matlab model, which can take into account also parasitic effects, has been derived and its accuracy has been verified. The model enables the designer to quickly optimize sizing in order to maximize bandwidth.