In this paper we present different ultra low-voltage CMOS carry generate circuits. The circuits may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuits show an improved performance compared to complementary CMOS in terms of delay. Preliminary results indicate a reduced delay to approximately 1/10 of a complementary CMOS design. Simulated data for a ST 90 nm CMOS process are included.