This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance. The proposed technique yields 9-14% energy reduction, with 10% area overhead. We will compare the proposed method with the-state-of-the art for reducing leakage current in domino logic circuits. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at 500 MHz is used as our test-bench.