Abstract:
We proposed optimal design of the post filter taps, for post filter + sequence detector receiver. The design is verified by detecting 56GBaud PDM-QPSK generated by commer...Show MoreMetadata
Abstract:
We proposed optimal design of the post filter taps, for post filter + sequence detector receiver. The design is verified by detecting 56GBaud PDM-QPSK generated by commercial CMOS DACs with 11GHz analog bandwidth. Only 2.6dB@1e-2 penalty is observed.
Date of Conference: 21-25 September 2014
Date Added to IEEE Xplore: 24 November 2014
Electronic ISBN:978-2-9549-4440-1
Print ISSN: 1550-381X
Contents 