Field-programmable gate arrays (FPGAs) are increasingly being used for implementing embedded systems. Soft-core processors for FPGAs are also becoming popular due to reduced design costs and better flexibility. Commercial soft-core processors such as Altera Nios II and Xilinx Microblaze have been widely deployed. While some research has been done exploring the design space of soft-core CPUs, much work remains to be done. In this paper we describe the design of UWindsor Nios II (UWN2), a soft-core processor that supports the same instruction set as Altera Nios II. We explore and evaluate different architectural variations of UWN2 including: (i) hardware versus software multiplication support (ii) register file implementation (iii) pipeline register implementation. We then compare UWN2's performance with Altera's Nios II and show that, with the recommended design implementations, our processor remains competitive. In future work we plan to integrate UWN2 with SCBuild, a CAD tool developed for automated design space exploration for CPU cores.