In Three-dimensional (3D) Integrated Circuit (IC), dummy TSVs are often required for thermal and thinning concerns. In this paper, we propose to use those “timing wasteful” dummy TSVs for timing optimization in on-chip memory, that is to replace bit line delay cells with dummy TSVs. The delay time is measured with different TSV sizes, TSV arrays, and technology nodes. Three memories are employed to verify the feasibility and reliability of the proposed technology.