Due to its reduced leakage and suppressed short channel effects, FinFET has been adopted by semiconductor industry to replace conventional bulk CMOS on most advanced process nodes. In this paper, performance of Predictive Technology Model (PTM) and BSIM-CMG models are investigated, and leakage reduction techniques are applied to adder circuit designs in order to minimize static power. HSPICE simulation results confirm significant leakage reduction with negligible performance penalty when power gating and zig-zag selection of sleep transistors are used simultaneously.