Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process | IEEE Conference Publication | IEEE Xplore

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process


Abstract:

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural...Show More

Abstract:

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90 nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.
Date of Conference: 28 August 2012 - 01 September 2012
Date Added to IEEE Xplore: 10 November 2012
ISBN Information:

ISSN Information:

PubMed ID: 23366924
Conference Location: San Diego, CA, USA

Contact IEEE to Subscribe

References

References is not available for this document.