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A high density, low leakage, 5T SRAM for embedded caches | IEEE Conference Publication | IEEE Xplore

A high density, low leakage, 5T SRAM for embedded caches


Abstract:

This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-S...Show More

Abstract:

This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV
Date of Conference: 23-23 September 2004
Date Added to IEEE Xplore: 15 November 2004
Print ISBN:0-7803-8480-6
Conference Location: Leuven, Belgium

References

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