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ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB | IEEE Conference Publication | IEEE Xplore

ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB


Abstract:

This work presents the design of a low noise amplifier (LNA) and programmable gain amplifier (PGA) set targeted for a fully integrated 3-5 GHz UWB transceiver in standard...Show More

Abstract:

This work presents the design of a low noise amplifier (LNA) and programmable gain amplifier (PGA) set targeted for a fully integrated 3-5 GHz UWB transceiver in standard 0.13 /spl mu/m CMOS. The circuit designs were optimized for best performance in terms of noise figure, linearity, gain, gain flatness, power consumption and ESD-hardness. For minimal crosstalk risk, differential designs with small areas were preferred. Measured LNA+PGA testchip shows a gain of 25.8 dB, with a gain flatness of 1 dB from 3-5 GHz, a NF of 3.6 dB at 3 GHz, an input compression point of -22.7dBm and an HBM ESD hardness of 1.5 kV at a total power consumption of 45 mW.
Date of Conference: 12-16 September 2005
Date Added to IEEE Xplore: 05 December 2005
Print ISBN:0-7803-9205-1
Print ISSN: 1930-8833
Conference Location: Grenoble, France

References

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