Abstract:
An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of ...Show MoreMetadata
Abstract:
An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of the traditional sense amplifier to reduce timing and design complexity. The focus of this paper is to demonstrate a memory array, comprised of 6T cells, that can generate near "rail-to-rail" bit-line voltage differentials that can be driven off macro without the aid of sense amplifiers. Therefore, short, low capacitance bit-line segments (or sub-arrays) are cascaded together to form larger bit-line structures, achieving performance and density goals with robust operation over a wide range of process and environmental conditions.
Date of Conference: 12-16 September 2005
Date Added to IEEE Xplore: 05 December 2005
Print ISBN:0-7803-9205-1
Print ISSN: 1930-8833