Abstract:
This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates (/spl rho/ > 1000/spl Omega//spl middot/cm). It demonstrates the drastic im...Show MoreMetadata
Abstract:
This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates (/spl rho/ > 1000/spl Omega//spl middot/cm). It demonstrates the drastic improvement in the varactors and inductors quality factor on these substrates. It stresses on the importance of optimizing the tank inductor and the VCO for high-resistivity substrates. A 5GHz VCO designed in a 0.13/spl mu/m partially depleted SOI CMOS confirms the low-power performance with a figure-of-merit greater than 190, placing this design at the top of the state-of-the-art.
Date of Conference: 12-16 September 2005
Date Added to IEEE Xplore: 05 December 2005
Print ISBN:0-7803-9205-1
Print ISSN: 1930-8833