Abstract:
A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in...Show MoreMetadata
Abstract:
A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-P 7-M CMOS technology. The 10-bit, 200-MSPS ADCs achieve DNL of 0.66 LSB, rNL of 1.00 LSB, and SNDR of 54.4 dB that corresponds to 8.7 ENOB. The power dissipation is only 55 mW from a 1.2-V supply.
Date of Conference: 12-16 September 2005
Date Added to IEEE Xplore: 05 December 2005
Print ISBN:0-7803-9205-1
Print ISSN: 1930-8833