A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology | IEEE Conference Publication | IEEE Xplore

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology


Abstract:

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a different...Show More

Abstract:

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps.
Date of Conference: 16-18 September 2003
Date Added to IEEE Xplore: 14 January 2004
Print ISBN:0-7803-7995-0
Conference Location: Estoril, Portugal

References

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