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Minimizing inductive noise in system-on-a-chip with multiple power gating structures | IEEE Conference Publication | IEEE Xplore

Minimizing inductive noise in system-on-a-chip with multiple power gating structures


Abstract:

A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a sy...Show More

Abstract:

A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off its sleep transistor. Experimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique.
Date of Conference: 16-18 September 2003
Date Added to IEEE Xplore: 14 January 2004
Print ISBN:0-7803-7995-0
Conference Location: Estoril, Portugal

References

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